The following options exist for downloading VITO. More information is available on the subset of implicit style behavioral Verilog supported by VITO, configuring VITO, and using VITO.
Permission to use, copy, modify and distribute this software and its documentation, for any purpose and without fee is hereby granted, provided that this permission notice appears prominently in supporting documentation and must be viewed prior to use, copying, modification or distribution. You are responsible for any modifications to the software which you make and notice that the software has been modified must be appended to this notice prior to further use, copying, modification or distribution.
This software is provided AS IS without warranty of any kind, including without limitation the warranties that the software is non-infringing, merchantable, or fit for a particular purpose, including high risk activities. The entire risk as to the quality and performance of the software is born by you. Should the software prove defective in any respect, you and not the developers, nor any parties associated with the developers, assume the entire cost of any service and repair.
This software may be subject to the Export Control Laws of the United States of America. It is your responsibility to determine the applicable laws and regulations and comply with them.
Original VITO was orignially available for both UNIX and DOS machines. (The DOS version used EZ-GCC. More information can be found at http://www.delorie.com .)
It is now only supported on Posix (UNIX/Linux/cygwin) environments.
The source code includes a makefile and is written in C. To compile VITO requires a C compiler and the language tools flex and Bison.
Assuming your computer has these (as Linux and cygwin usually do), it is easy to install version 3.1 (or later). After downloading the vito31.tar file, you need to tar -xf vito31.tar . Then do cd vito31 followed by make; optionally you may test your installation with ./testinstall.
The DOS versions are 16-bit executables, and only work under older (16- or 32- bit) versions of Windows at a command prompt. Versions 1.1 and 1.2 use the code generation documented in Verilog Digital Computer Design.
Comments, suggestions, or bug reports may be sent to the username "bugs" at the address derived from this website name.
ARM, Parallax, BasicStamp, CUDA, Nvidia, Synopsys, Design Compiler and Verilog are trademarks of their respective owners.
Last updated on 4 Feb 2013