The output of VITO is intended to be submitted to a commercial synthesis tool. VITO passes through many parts of the original Verilog unmodified. Whether what VITO passes through synthesizes to the desired hardware depends on the synthesis tool.
The parallel processing statements ( wait and fork) were not supported in original VITO, but were added in version 1.3. This feature is not supported in other VITO tools, like VITOCUDA.
Features, such as -> and deassign statement are not implemented by VITO and are typically not supported by synthesis tools.
Some features that VITO passes through may be supported by some synthesis tools, but not by others. For example, division by a variable is supported by some vendors, but not by others.