In 1999, to show that VITO is powerful enough to work with realistic designs, Mark Arnold together with Freddy Engineer and Mark Winkel (the AWE team) developed the ARM Workalike Experiment (authors and acronym are both AWE). AWE is a clone of as much of a full-featured ARM architecture as we could do without infringing on ARM's patents. AWE was presented at WESCON in 1999, and several enhanced versions were used in academic experiments ( see papers ) Our initial premise was VITO made the design of AWE much easier than if we used explicit-style Verilog; much later (2007) S. Langhanoja demonstrated AWE synthesized to be both smaller and faster than a similar clone designed with traditional explicit-style Verilog.
VITO is able convert the implicit-style source for the AWE into synthesizable Verilog; VITOCUDA is able to simulate the AWE on a GPU. The other VITO tools lack support for functions, and therefore are not compatible with the AWE source. The source file (awe812cpu.v) for the AWE is in the examples directories of VITO 3.1 and VITOCUDA 3.1.
This site is maintained by Mark Gordon Arnold, co-designer of the original VITO, and author of Verilog Digital Computer Design: Algorithms into Hardware, (1999, Prentice Hall PTR). Thanks to all who helped use and improve VITO, including: T. Bailey, E. Chester, J. H. Cho, J. Cowles, J. Cupal, F. Engineer, S. Langhanoja, D. Luksenberg, N. Sample, J. Shuler (original VITO's other co-designer), P. Vouzis and M. Winkel.
ARM, Parallax, BasicStamp, CUDA, Nvidia, Synopsys, Design Compiler, Xilinx, Virtex and Verilog are trademarks of their respective owners.
Updated 11 Feb 2013.